According to the study by the inventors of the present invention, the technologies described below are known as the technologies for the defect relief in a memory.
For example, the method of the operation for the defect relief of a word line described below is known. That is, the address is first confirmed and the decoding is performed after the confirmation, and then, the normal word line or the redundant word line is activated. However, the operation speed is reduced due to the address confirmation in this method. For its prevention, the technologies described in Japanese Patent Application Laid-Open No. 2-21500 and 4-345998 have been developed.
For example, Japanese Patent Application Laid-Open No. 2-21500 discloses the memory device capable of reducing the access time delay in the read operation from the redundant memory array. More specifically, in the read operation of this memory device, the word line in the normal memory array and the redundant word line in the redundant memory array are simultaneously activated, and the relief or the non-relief is determined before each of the read data reaches the sense amplifier, and then, the data of the sense amplifier in accordance with the result of the determination is selected and outputted to the data bus. This memory device is particularly effective when applied to a static RAM (SRAM).
Also, Japanese Patent Application Laid-Open No. 4-345998 discloses the memory device capable of reducing the access delay due to the defect relief without remarkably increasing the power consumption and the circuit area. More specifically, in the operation of this memory device, only the normal word line is activated and the read data thereof is connected to the sense amplifier via a switch in the non-relief operation. Meanwhile, in the relief operation, the redundant word line provided in the memory mat different from that of the normal word line is activated together with the normal word line and only the read data of the redundant word line is connected to the sense amplifier via another switch. Note that this memory device is particularly effective when applied to the dynamic RAM (DRAM).